Semiconductor electronics is central to both CBSE board exams and competitive tests (JEE/NEET) because it combines quantum-level material properties with circuit-level reasoning. Mastery of PN junction physics, carrier transport, diode/LED/Zener behaviour and BJT operation allows students to solve a wide variety of numerical, graph-interpretation and conceptual problems that frequently appear in higher-weight questions.
This chapter develops problem-solving skills used in device modelling (Shockley equation, depletion capacitance, small‑signal resistance), data interpretation (Arrhenius plots, semilog I–V), and design/analysis of bias networks and protection circuits. Practising multi-step numerical and assertion–reason problems from this topic sharpens the analytical reasoning required in board exams and competitive tests.
15
Minutes
10
Questions
1 / -0
Marking Scheme
Q1. An abrupt silicon PN junction at K has and . Using and V, compute the built‑in potential from . (Nearest value)
Q2. Statement‑I: Under steady uniform optical illumination of an intrinsic semiconductor the excess carrier concentrations satisfy , and the conductivity increment is .
Statement‑II: Photons create equal electron–hole pairs but since in most semiconductors the numerical change in conductivity is dominated by electrons even though .
Q3. A silicon diode at K has reverse saturation current A. Using the Shockley equation with V, estimate the forward current at V. (Closest)
Q4. On a semilog plot (natural log) of forward current vs forward voltage at K, two diodes P and Q show linear regions with slopes and where . Using , identify , and the dominant transport mechanism in P and Q.
Q5. Two reverse‑biased silicon diodes X and Y show sharp breakdowns at approximately V and V respectively. Experimentally, when temperature increases, decreases while increases. Which statement best explains the observations?
Q6. For the circuit: V, k (to base from ), k (base to ground), k (collector to ). Take V and . Using Thevenin for the base divider, determine the operating condition and approximate collector current.
Q7. Statement‑I: For an ‑type semiconductor, increasing temperature moves the Fermi level toward the mid‑gap (away from the conduction band edge).
Statement‑II: As temperature rises the intrinsic concentration increases, making the dopant contribution relatively less important; thus approaches the intrinsic level , explaining the shift.
Q8. An intrinsic semiconductor sample shows conductivities at K and at K. Assuming intrinsic conduction with , estimate the band gap (use ). (Nearest)
Q9. A diode biased at V has DC current mA and ideality factor . It is in series with . Using V and small‑signal resistance , a small increment mV is applied to the source. Using the small‑signal model, estimate the incremental diode current .
Q10. Two diodes D1 and D2 are in series and share the same forward current . For K the parameters are: D1: , A; D2: , A. They are forward biased together so that V. Neglecting the “−1” in the diode equation, solve approximately for and determine which diode drops the larger voltage.